The present invention is related to a control circuit of a semiconductor switch provided between a DC power supply and a load, for protecting the semiconductor switch which turns ON/OFF the load from a shortcircuit current. More specifically, the present invention is directed to a technique capable of specifying a circuit where a shortcircuit/grounding event happens to occur and of cutting off this specified circuit in such a case that a plurality of loads and a plurality of semiconductor switches are provided with respect to the same DC power supply.
Loads (electric appliances) such as, for instance, a motor for driving a power window, or a lamp, which are mounted on a vehicle are driven by applying a DC voltage from a battery functioning as a DC power supply to the own loads. In this case, since a semiconductor switch such as a MOSFET and the like, which is provided between a load and the battery, is turned ON/OFF, this load is controlled to be driven/stopped.
Also, in a case that an overcurrent protecting apparatus is mounted on a vehicle, an overcurrent protecting apparatus immediately turns OFF the semiconductor switch for protecting both a circuit and a load when the overcurrent flows through the semiconductor switch. Such an overcurrent protecting apparatus is known from, for example, JP-A-2000-253560.
FIG. 6 is a circuit diagram for indicating an arrangement of the overcurrent protecting apparatus described in JP-A-2000-253560. As shown in FIG. 6, the overcurrent protecting apparatus has two sets of an N type MOSFET TA and an N type MOSFET TB as a semiconductor switch, which constitute a multi-source FET. Drains of the respective MOSFETs TA and TB are connected to a plus terminal of a DC power supply VB.
Also, a source of the MOSFET TA is connected via a load (RL) to a minus terminal (ground) of the DC power supply VB. On the other hand, a source of the MOSFET (TB) is grounded via a resistor Rr. A transition component resistor R10 is arranged parallel to the resistor Rr in order to properly accept a rush current. This rush current is produced during transition condition when a lamp is loaded.
Also, the overcurrent protecting apparatus has a comparator CMP10, and a latch DF100 provided on the side of an output of this comparator CMP10. The comparator CMP10 compares a source voltage VSA of the MOSFET TA with a source voltage VSB of the MOSFET TB in voltage levels. An output terminal of the latch DF100 is connected to one of input terminals of an AND circuit AND100.
Further, the overcurrent protecting apparatus has a switch SW100 and a resistor R102, which are employed so as to turn ON/OFF the MOSFETs TA and TB. One terminal side of the switch SW100 is connected to a power supply VB, and the other terminal side of the switch SW100, namely a junction point between the other terminal of the switch SW100 and the resistor R102 is connected to the other input terminal of the AND circuit AND100.
The output terminal of the AND circuit AND100 is connected to a driver circuit 100, and an output terminal of this driver circuit 100 is connected via a resistor R100 to a gate of the MOSFET TA and a gate of the MOSFET TB.
The transition component resistor R10 is connected to the circuit of the overcurrent protecting apparatus for a time period during which a rush current flows through a load RL, namely only for a predetermined time duration from a time instant when the switch SW100 was turned ON, and thereafter, is cut out from the circuit. The latch DF100 is reset when the switch SW100 is turned OFF, and an output signal of this latch DF100 becomes an H level.
Next, operations of the overcurrent protecting apparatus will now be explained. Since the two input signals of the AND circuit AND100 become H levels when the switch SW100 is turned ON, the output signal of the AND circuit AND 100 becomes an H level, and the driver circuit 100 supplies a charge pump voltage to the gate “G” (namely common gates of respective MOSFETs TA and TB) of the multi-source FET.
As a result, the respective MOSFETs TA and TB are brought into ON states, a load current “ID” flows through the MOSFET TA, and at the same time, a reference current “Iref” flows through the MOSFET TB.
In this case, the MOSFET TB is set to have the same characteristic as that of the MOSFET TA, and normally, a channel width of the MOSFET TB is set to 1/1000 to 1/2000 of a channel width of the MOSFET TA. As a consequence, assuming that (channel width of TA)/(channel width of TB)=n, “n” is nearly equal to 1000 to 2000. Then, assuming that the source voltages of the MOSFETs TA and TB are “VSA” and “VSB”, when VSA=VSB, the load current ID is defined as ID=n*Iref.
The magnitude of the voltage VSA depends upon the resistance of the load resistor RL, whereas the magnitude of the voltage VSB depends upon either a resistor Rr, or a combined parallel resistance composed of the resistor Rr and the transition component resistor R10. Under such a condition that both the wiring line and the load are set to the normal conditions, both the resistor Rr and the transition component resistor R10 are set in such a manner that VSA>VSB while the rush current flowing time period is included. As a result, the output signal of the comparator CMP10 is held at an L level under normal condition.
At this time, when the wiring line connected between the MOSFET TA and the load RL is shortcircuited/grounded due to some reasons, the drain current ID of the MOSFET TA is rapidly increased, and thus, the source voltage VSA of the MOSFET TA becomes smaller than the source voltage VSB of the MOSFET TB, so that the output signal (L level) of the comparator CMP10 is changed into H level, and also, the output signal (H level) of the latch DF100 is switched to an L level. As a result, the output signal of the AND circuit AND100 becomes an L level, the output terminal side of the driver circuit 100 is grounded, and also, the gate G of the multi-source FET is grounded via the resistor R100, so that the MOSFETs TA and TB are turned OFF. As a consequence, the shortcircuit current flowing through the MOSFET TA is cut out, so that both the wiring line and the MOSFET TA can be protected.
FIG. 7 is a characteristic diagram for representing a change of the current ID in such a case that when a rush current does not flow, namely the load RL is set under the normal condition, the wiring line between the MOSFET TA and the load RL is shortcircuited to be grounded.
As shown in FIG. 7, when the load current ID under the normal condition flows through the circuit of the overcurrent detecting apparatus, if a shortcircuit/grounding event happens to occur at a time instant constituting a point A1, the current ID rapidly starts to be increased. Assuming that a resistance of the wiring line through which the current ID flows is equal to “Rw”, an inductance of this wiring line is “Lw”, a drain-to-source resistance of the MOSFET TA is “RonA”, the power supply voltage is “VB”, and an internal resistance of the power supply is “Rbatt”, the current ID flowing when the shortcircuit happens to occur is increased based upon an exponential function curve of a time constant “τ1” which is expressed by the below-mentioned equation (2), while a current value “ID1” indicated by the below-mentioned equation (1) is defined as a target value.ID1=VB/(RonA+Rw+Rbatt)  (1)τ1=Lw/(RonA+Rw+Rbatt)  (2)
Then, when the present time exceeds such a time instant constituting a point A2, the current ID becomes ID≧n*Iref, so that the multi-source FET is cut off. In this case, the gate G of the multi-source FET is grounded via the resistor R100, so that electric charges are discharged which is stored in the gate G. In this case, if a gate capacitance of this gate G is assumed as “Cg”, then a discharge time constant becomes Cg*R100.
Since the gate-to-source voltage VGSA of the MOSFET TA is reached to approximately 10 V before being cut off, a finite time is required until the discharging operation of the gate electrons are accomplished. When the gate-to-source voltage VGSA is lowered due to the gate discharge operation, the drain-to-source resistance RonA of the MOSFET TA is increased.
In other words, although the resistance RonA is constant until the time instant of the point A2, this resistance RonA is increased when the time instant A2 elapses, so that the current ID1 shown in the above-described equation (1) becomes small, and the same time, the time constant “τ1” is also decreased. As a result, the current ID is increased in a linear manner which is deviated from the expositional function, and then, is reached to a peak current at a time instant constituting a point A3. The faster the gate electrons of the multi-source FET are discharged, namely, the smaller the resistor R100 is decreased, the faster the time instant is reached to the point A3, so that the peak value of the current ID becomes low. Since the increase of the resistor RonA is continued, when the time instant of the point A3 has elapsed, the current ID is decreased and becomes zero at a time instant constituting a point A4.
FIG. 8 is a characteristic diagram for representing a change of the current ID in such a case that a shortcircuit/grounding event (failure) happens to occur during a transition period just after the switch SW1 is turned ON, namely while the transition component resistor R10 is being connected parallel to the resistor Rr. In this drawing, a curved line indicated by a two-dot and dash line represents a change of the current ID under such a normal condition that a shortcircuit/grounding event does not occur. In this drawing, the current ID corresponds to a so-called “rush current”, and this rush current may be reached to such a peak current value which becomes larger than the current ID under normal condition by 5 to 10 times.
Then, in order to avoid such an erroneous judgement that this rush current is recognized as a shortcircuit current, a shortcircuit current judging value (n*Iref) is set to such a value which is larger than the peak value of the rush current. In other words, in FIG. 8, a dashed line for indicating (n*Iref) is set to become larger than the peak value of the rush current indicated by the two-dot dash line. In this case, in order to set the reference current Iref to a large value, the transition component resistor R10 is additionally connected parallel to the resistor Rr for a predetermined time (namely, rush current flowing time period).
When a shortcircuit/grounding event happens to occur at a point B1 of FIG. 8, the current ID is rapidly increased, the multi-source FET is cut off at a point B2, and the current ID is increased up to a point B3, and thereafter, the current ID is decreased. The operations are resembled to the above-described operation case of FIG. 7. The point B1 to B4 of FIG. 8 correspond to the points A1 to A4 of FIG. 7.
A different point between FIG. 7 and FIG. 8 is the magnitude of the current Iref. In FIG. 8, since the shortcircuit current judging value (n*Iref) is set to such a value which exceeds the rush current, when the multi-source FET is cut off, namely the current ID at the point B2 is increased, the peak value (point B3) of the shortcircuit current is increased. Until the point B2 where the MOSFET TA is turned ON, the source-to-drain voltage becomes a small value, so that even when a large current flows, a power loss of this MOSFET TA is small.
Then, when the present time passes through the point B2, the MOSFET TA is turned OFF, so that the source-to-drain voltage thereof is increased. If a large current flows under this condition, then a power loss of the MOSFET TA is increased. In FIG. 7, since the peak value of the shortcircuit current at the point A3 is small, the power loss is relatively small. In the case of FIG. 8, since the current ID is increased after the present time has passed through the point B2, the power loss of the MOSFET TA becomes large value, which may cause a temperature of the channel of this MOSFET TA to be increased. Since a time period from the point B1 to the point B4 during which the shortcircuit current flows corresponds to such a short time period shorter than, or equal to 300 [μsec], the increase in the channel temperature of the MOSFET TA may be restricted by a transition thermal resistance.
Since the transition thermal resistance of this time range is determined by a chip size, an element having a large chip size must be used in order to suppress an increase of a channel temperature caused by a shortcircuit current. In other words, such an element having a small chip size cannot be used, so that a design freedom is restricted, which may cause a cost-up factor.
Also, there is another problem in fluctuations of the reference current Iref. That is, in order to avoid that the MOSFET TA is erroneously cut off by the rush current, the following measures must be taken, namely, the precision of the rush current judging value is increased, or an interval between the peak value of the rush current and the judging value is sufficiently widened. Any of these solving methods may cause the cost-up factor. As another solving method, one method has been proposed in which an overheat interrupting function capable of detecting an overheat condition of a semiconductor element to interrupt a current is additionally provided so as to protect an FET. Similarly, this solving method may cause the cost-up factor.
Furthermore, in the case that plural sets of loads such as electric appliances have been provided, circuits which constitute a total channel number in correspondence with a total number of loads must be employed. As a result, there is such a problem that the construction of the apparatus becomes bulky.
As previously explained, in the related overcurrent protecting apparatus, the discrimination of the shortcircuit current under the normal condition from the shortcircuit current under the abnormal condition is carried out by detecting the difference in the levels of the currents which flow through the MOSFET. As a result, when the peak value of the rush current is increased, the time required to be reached to the judging value is prolonged, so that the judgement as to the occurrence of the shortcircuit is delayed, and therefore, the timing when the shortcircuit current is cut off is delayed. As a consequence, the power loss of the semiconductor element is increased, so that such a problem may occur. That is, the temperature increase of the semiconductor element is enlarged.
Furthermore, the technique disclosed in JP-A-2000-253560 does not describe operations executed in the case that there are a plurality of FET channels which are connected to the DC power supply.